1. Field of the Invention
The present invention relates to an element substrate, a printhead, and a printing apparatus, particularly to, for example, a full-line printhead which includes an element substrate integrated thereon and prints in accordance with an inkjet method and a printing apparatus for printing by using the same. The present invention more specifically relates to a printhead including an element substrate in which a plurality of printing elements and a driving circuit configured to drive the printing elements are provided on the single element substrate and a printing apparatus.
2. Description of the Related Art
For example, as information output apparatuses such as a word processor, a personal computer, and a facsimile apparatus, in general, printing apparatuses for printing any desired information such as characters and images on a sheet-like print medium such as a paper sheet or a film are widely used.
Some of these printing apparatuses use an inkjet printhead (to be referred to as a printhead hereinafter) that prints using thermal energy. This printhead includes printing elements (heaters) provided at portions communicating with orifices for discharging ink droplets. A current is supplied to the printing elements to cause the heaters to generate heat. Ink droplets are discharged by film boiling of ink, and printing is performed. Such a printhead can arrange a number of orifices and printing elements (heaters) at high densities, and a high-resolution image can thus be printed.
FIG. 14 is a circuit diagram showing the arrangement of an element substrate integrated on a conventional inkjet printhead.
As shown in FIG. 14, an element substrate 101 is connected to a main body circuit 200 of a printing apparatus via a power cable 140. A heater voltage VH is thus applied to a plurality of heaters (printing elements) 111 via a pad 130. Note that a ground voltage GNDH is applied to a pad 131. An ASIC 107 of the main body circuit 200 supplies a data signal (DATA), a clock signal (CLK), a latch signal (LT), and a heat enable signal (HE) to logic circuits 114 via a signal cable 141 and pads 135 to 138. Note that the plurality of logic circuits 114 have the same circuit arrangement including a flip-flop circuit 118, a latch circuit 119, and an AND circuit 120.
In each logic circuit 114, the flip-flop circuit 118 receives the data signal (DATA) input in synchronism with the clock signal (CLK). The data signal (DATA) received by the flip-flop circuit 118 is received and held by the latch circuit 119 in synchronism with the latch signal (LT) input via the pad 135. On the other hand, the heat enable signal (HE) that defines a heater driving period is input to the pad 136. The AND circuit 120 obtains the logical product (AND) between the heat enable signal (HE) and the output of the latch circuit 119, and outputs the result to a level converter (LVC) 122 as a selection signal.
The element substrate 101 includes an enormous number of elements to be driven, as compared to the element substrate of a general power device. The number of printing elements (heaters) 111 connected to a heater power supply 102 is several thousands to ten thousand per substrate. Since corresponding driving elements 112 are provided as many as the heaters 111, the number of level converters 122 essential to drive the driving elements 112 is enormous as well. For this reason, power consumption of the level converters 122 leads to heat generation from the element substrate 101, greatly affecting the print characteristic. Hence, a 2-input circuit of a differential input type, which consumes no standby power, is widely used as the level converter (LVC) 122.
To meet a recent requirement to speed up an inkjet printing apparatus, the number of driven heaters per unit time increases. The main body circuit 200 includes a large-capacitance capacitor 103 to stabilize the power supply, thereby implementing stable power supply. In addition, a capacitor 105 is provided for a logic circuit power supply 104 as well for stable voltage supply.
However, in a case where a large-capacitance capacitor is provided, to turn off the power supply voltage takes time.
FIG. 15 is a graph showing time-rate changes in voltage drop of the heater voltage VH and a logic voltage VDD after power shutdown.
As shown in FIG. 15, when the main body circuit 200 is shut down due to, for example, a power failure (t=t1), a state in which a voltage is applied to the heaters 111 continues long until charges accumulated in the capacitor 103 are discharged. For this reason, it is necessary to continuously control the driving elements 112 so as not to supply an unwanted current to the heaters 111 as much as possible until the heater voltage VH drops to “0” (t=t3).
As an arrangement for preventing supply of an unwanted heater current, Japanese Patent No. 4,266,460 proposes a circuit arrangement in which a logic circuit has a reset function. In a state in which a logic power is applied (t=t0 to t1), this arrangement enables control to reliably inhibit supply of an unwanted heater current by inputting a RESET signal. Upon power shutdown (t=t1), however, the logic circuit power supply 104 completes discharge in a short period of time (t=t2), as shown in FIG. 15, because the voltage is lower than that of the heater power supply, and the capacitor 105 has a relatively small capacitance. For this reason, control by the RESET signal is immediately disabled.
On the other hand, the 2-input level converter 122 is operable even after shutdown of the logic circuit power supply 104 because the power is received from the heater power supply 102. However, when the logic voltage VDD supplied via a pad 134 drops to 0 V, and consequently, all signals from the logic circuit 114 change to 0 V, the level converter (LVC) 122 receives in-phase logics (both 0 V), and its output logic becomes indefinite.
FIGS. 16A and 16B are views respectively showing the circuit arrangement and the input/output relationship of the 2-input level converter 122.
FIG. 16A is a circuit diagram showing the arrangement of the 2-input level converter 122. Referring to FIG. 16A, INB and IN represent inputs (terminals); and OUT, an output (terminal). As is apparent from comparison of FIGS. 14 and 16A, the 2-input level converter 122 receives the heater voltage VH via the pad 130, and is connected to a ground voltage VSS via a pad 133. The 2-input level converter 122 is formed from six MOSFETs.
In the above arrangement, when power is shut down as both logic voltages VDD from the logic circuit 114 become 0 V (that is, both IN and INB are at Low state), and the heater voltage VH becomes “0”, both NMOSs 401 are turned off, and the gate voltages of both PMOSs 402 float. As a result, the output becomes indefinite. This corresponds to a state shown in FIG. 16B in which IN and INB are Low, and OUT is indefinite.
Hence, during the period of t=t2 to t3 in FIG. 15, if the driving elements 112 cannot be controlled, and voltages of nodes whose states are indefinite change to 0 V or more, an unwanted current may flow to the heaters. For the above-described reasons, no expected effect can be obtained by the arrangement proposed in Japanese Patent No. 4,266,460 in case of power shutdown or the like.
To solve this problem, Japanese Patent No. 4,183,226 proposes an arrangement that powers off a driving circuit portion for controlling the gate voltages of driving elements, thereby setting the input (gate) voltages of the driving elements 112 to 0 V and reliably preventing an unwanted heater current from flowing. However, this arrangement requires power to the driving circuit portion to be supplied from the heater voltage VH via a stepdown circuit. The conventional arrangement as shown in FIG. 14, which includes no stepdown circuit, cannot meet this requirement.